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1 m e m o r y all data sheets are subject to change without notice (619) 503-3300 - fax: (619) 503-3301 - www.maxwell.com 16 megabit (512k x 32-bit) 89lv1632 ?2005 maxwell technologies. all rights reserved. low voltage mcm sram 08.18.05 rev 3 f eatures : ? four 512k x 8 sram die r ad -p ak ? technology hardens against natural space radia- tion technology total dose hardness: - > 100 krad (si), depending upon space mission excellent single event effects: - sel > 101mev-cm 2 /mg - seu threshold = 3 mev-cm 2 /mg - seu saturated cross section: 8e-9 cm 2 /bit package: 68-pin quad flat package completely static memory - no clock or timing strobe required internal bypass capacitor high-speed silicon-gate cmos technology 3.3 v 10% power supply equal address and chip enable access times three-state outputs all inputs and outputs are ttl compatible d escription : maxwell technologies? 89lv1632 high-performance 16 mega- bit multi-chip module (mcm) static random access memory features a greater than 100 krad(si) total dose tolerance, depending upon space mission. the four 4-megabit sram die and bypass capacitors are incorporated into a high-reliable hermetic quad flat-pack ceramic package. with high-perfor- mance silicon-gate cmos technology, the 89lv1632 reduces power consumption and eliminates the need for external clocks or timing strobes. it is equipped with output enable (oe ) and four byte chip enable (cs1 - cs4 ) inputs to allow greater system flexibility. when oe input is high, the output is forced to high impedance. maxwell technologies' patented r ad -p ak ? packaging technol- ogy incorporates radiation shielding in the microcircuit pack- age. in a geo orbit, r ad -p ak ? packaging provides greater than 100 krad(si) total radiation dose tolerance, dependent upon space mission. it eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or a space mission. this product is available in with screening up to maxwell technologies self-defined class k. cs 1-4 mcm oe, we address 4mb sram 4mb sram 4mb sram 4mb sram power ground i/o 0-7 i/o 8-15 i/o 16-23 i/o 24-31 16 megabit (512k x 32-bit) sram mcm logic diagram 89lv1632
m e m o r y 2 all data sheets are subject to change without notice ?2005 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit)low voltage mcm sram 89lv1632 08.18.05 rev 3 t able 1. p inout d escription p in s ymbol d escription 34-28, 42-36, 62-64, 7, 8 a0-a18 address enable 65 we writeenable 66 oe output enable 3-6 cs1 - cs4 chip enable 43-46, 48-51,53-56, 58-61, 9-12, 14-17, 19-22, 24-27 i/o0-i/o31 data input/output 2, 67, 68 nc no connection 1, 18, 35, 52 v cc +3.3v power supply 13, 23, 47, 57 v ss ground t able 2. 89lv1632 a bsolute m aximum r atings (v oltage referenced to v ss = 0v) p arameter s ymbol m in m ax u nits power supply voltage relative to v ss v cc -0.5 +7.0 v voltage relative to v ss for any pin except v cc v in , v out -0.5 v cc +0.5 v weight 42 grams thermal resistance f jc 3.6 c/w power dissipation p d -- 4.0 w operating temperature t a -55 +125 c storage temperature t s -65 +150 c t able 3. 89lv1632 r ecommended o perating c onditions (v cc = 3.3+ 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter s ymbol m in m ax u nits supply voltage, (operating voltage range) v cc 3.0 3.6 v input high voltage v ih 2.2 v cc + 0.5 (1) 1. v ih (max) = v cc + 2v ac (pulse width < 10ns) for i < 80 ma. v input low voltage v il -0.5 (2) 2. v il (min) = -2.0v ac; (pulse width < 20 ns) for i < 80 ma. 0.8 v
m e m o r y 3 all data sheets are subject to change without notice ?2005 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit)low voltage mcm sram 89lv1632 08.18.05 rev 3 t able 4. 89lv1632 d elta l imits p arameter v ariationl i cc + 10% of stated value in table 5 i sb + 10% of stated value in table 5 i sb1 + 10% of stated value in table 5 i li + 10% of stated value in table 5 t able 5. 89lv1632 dc e lectrical c haracteristics (v cc = 3.3+ 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter s ymbol t est c onditions s ubgroups m in t yp m ax u nits input leakage current i li v in = 0 to v cc 1, 2, 3 -8.0 -- +8.0 ua output leakage current i lo cs = v ih , v out = v ss to v cc 1, 2, 3 -8.0 -- +8.0 ua average operating current cycle time: 35 ns i cc min. cycle, 100% duty, cs = v il , i out = 0 ma v in = v ih or v il 1, 2, 3 -- -- 640 ma standby power supply current i sb cs = v ih , min cycle 1, 2, 3 -- -- 240 ma cmos standby power supply current i sb1 cs > v cc - 0.2v, f = 0 mhz, v in > v cc - 0.2v or v in < 0.2v 1, 2, 3 -- -- 40 ma output low voltage v ol i ol = + 8.0 ma 1, 2, 3 -- -- 0.4 v output high voltage v oh i oh = -4.0 ma 1, 2, 3 2.4 -- -- v input capacitance 1 cs1 - cs4 , oe , we i/o0-7, i/o8-15, i/o16-23, i/o24-31 a0 - a18 1. guaranteed by design. c in v in = 0 v 4, 5, 6 7 28 7 7 28 pf output capacitance 1 c out v i/o = 0 v 4, 5, 6 8 pf t able 6. 89lv1632 ac o perating c onditions and c haracteristics (v cc = 3.3+ 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter m in t yp m ax u nits input pulse level 0.0 -- 3.0 v output timing measurement reference level -- -- 1.5 v
m e m o r y 4 all data sheets are subject to change without notice ?2005 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit)low voltage mcm sram 89lv1632 08.18.05 rev 3 input rise/fall time -- -- 3.0 ns input timing measurement reference level -- -- 1.5 v t able 7. 89lv1632 r ead c ycle (v cc = 3.3+ 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter s ymbol s ubgroups m in t yp m ax u nits read cycle time -30 t rc 9, 10, 11 30 -- -- ns address access time -30 t aa 9, 10, 11 -- -- 30 ns chip select to output -30 t co 9, 10, 11 -- -- 30 ns output enable to output -30 t oe 9, 10, 11 -- - -- 14 ns output enable to low-z output -30 t olz 9, 10, 11 -- 0 -- ns chip enable to low-z output -30 t lz 9, 10, 11 -- 3 -- ns output disable to high-z output -30 t ohz 9, 10, 11 -- 8 -- ns chip disable to high-z output -30 t hz 9, 10, 11 -- 8 -- ns output hold from address change -30 t oh 9, 10, 11 3---- ns chip select to power up time -30 t pu 9, 10, 11 -- 0 -- ns chip select to power downtime -30 t pd 9, 10, 11 -- 20 -- ns t able 8. 89lv1632 f unctional d escription cs we oe m ode i/o p in s upply c urrent hx 1 1. x = don?t care. x 1 not select high-z i sb , i sb1 l h h output disable high-z i cc l h l read d out i cc llx 1 write d in i cc t able 6. 89lv1632 ac o perating c onditions and c haracteristics (v cc = 3.3+ 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter m in t yp m ax u nits
m e m o r y 5 all data sheets are subject to change without notice ?2005 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit)low voltage mcm sram 89lv1632 08.18.05 rev 3 t able 9. 89lv1632 w rite c ycle (v cc = 3.3+ 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter s ymbol s ubgroups m in t yp m ax u nits write cycle time -30 t wc 9, 10, 11 30 -- ns chip select to end of write -30 t cw 9, 10, 11 20 -- ns address set-up time -30 t as 9, 10, 11 0-- ns address valid to end of write -30 t aw 9, 10, 11 20 -- ns write pulse width (oe high) -30 t wp 9, 10, 11 20 -- ns write pulse width (oe low) -30 t wp1 9, 10, 11 30 -- ns write recovery time -30 t wr 9, 10, 11 0-- ns write to output high-z -30 t whz 9, 10, 11 -- 9 -- ns data to write time overlap -30 t dw 9, 10, 11 14 -- ns data hold from write time -30 t dh 9, 10, 11 0-- ns end write to output low-z -30 t ow 9, 10, 11 -- 3 -- ns
m e m o r y 6 all data sheets are subject to change without notice ?2005 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit)low voltage mcm sram 89lv1632 08.18.05 rev 3 f igure 1. ac t est l oads f igure 2. t iming w aveform of r ead c ycle (1) (a ddress c ontrolled ) f igure 3. t iming w aveform of r ead c ycle (2) (we = v ih ) 1. we is high for read cycle. 2. all read cycle timing is referenced from the last valid address to the first transition address. + 3.3v
m e m o r y 7 all data sheets are subject to change without notice ?2005 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit)low voltage mcm sram 89lv1632 08.18.05 rev 3 3. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage conditions, t hz (max) is less than t lz (min) both for a given device and from device to device. 5. transition is measured + 200mv from steady state voltage with load(b). this parameter is sampled and not 100% tested. 6. device is continuously selected with cs = v il . 7. address valid prior to coincident with cs transition low. 8. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. f igure 4. t iming w aveform of w rite c ycle (1) (oe c lock )
m e m o r y 8 all data sheets are subject to change without notice ?2005 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit)low voltage mcm sram 89lv1632 08.18.05 rev 3 f igure 5. t iming w aveform of w rite c ycle (2) (oe l ow f iixed ) f igure 6. t iming w aveform of w rite c ycle (3) (cs c ontrolled ) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low cs and we . a write begins at the latest transition cs going low and we going low. a write ends at the earliest transition cs going high or w e going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs or we going high. 6. if oe , cs and we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization of elimination of bus contention conditions is necessary during read and write cycle. 8. if cs foes low simultaneously with we going or after we going low, the outputs remain high impedance state. 9. d out is the read data of the new address. 10.when cs is low, i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied.
m e m o r y 9 all data sheets are subject to change without notice ?2005 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit)low voltage mcm sram 89lv1632 08.18.05 rev 3 f igure 7. sram h eavy i on c ross s ection f igure 8. sram p roton seu c ross s ection s tatic
m e m o r y 10 all data sheets are subject to change without notice ?2005 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit)low voltage mcm sram 89lv1632 08.18.05 rev 3 q68-04 note: all dimensions in inches 68 p in r ad -p ak ? q uad f lat p ackage s ymbol d imension m in n om m ax a 0.206 0.225 0.244 b 0.015 0.017 0.018 c 0.008 0.009 0.12 d 1.479 1.494 1.509 d1 0.800 e 0.050 bsc s1 -- 0.339 -- f1 1.239 1.244 1.249 f2 1.429 1.434 1.439 l 2.485 2.510 2.545 l1 2.485 2.500 2.505 l2 1.690 1.700 1.710 a1 0.180 0.195 0.210 n68
m e m o r y 11 all data sheets are subject to change without notice ?2005 maxwell technologies. all rights reserved. 16 megabit (512k x 32-bit)low voltage mcm sram 89lv1632 08.18.05 rev 3 important notice: these data sheets are created using the chip manufacturers published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the use of this information. maxwell technologies? products are not authorized for use as critical components in life support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.

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